Currently, in-memory management systems are being designed to rely on primary data residency in system memory (e.g., volatile byte-addressable random access memory (RAM)) and primary data persistence in low-latency non-volatile, byte-addressable memory to achieve lower access latencies for primary data used to execute various types of applications (e.g., database application). In-memory management systems typically implement virtual memory management schemes in which virtual memory addresses that are referenced by an application or process are mapped into physical addresses in memory. A memory management unit (MMU) allows a processor to efficiently manage physical memory by creating one or more sparse virtual address spaces that can translate to sparse physical addresses. A MMU divides virtual and physical memory into pages, where pages can range in size from 4 Kbyte to larger size pages (e.g., megabyte or gigabyte). An MMU will utilize page table entries (PTEs), which are stored in page tables, to perform virtual-to-physical address translation operations, and utilize control and flag information within the PTEs to determine caching, permissions, access rights, and other information for individual pages within a virtual address space.
With conventional virtual memory management schemes, it is difficult and expensive for an operating system or hypervisor to efficiently measure memory utilization for pages that are mapped into a translation lookaside buffer (TLB). For example, a conventional PTE data structure includes a single “accessed” bit which provides a flag that is used by the operating system to mark a given page as having been accessed when, for example, the PTE is mapped into a TLB. However, the single “accessed” bit does not provide specific information regarding the frequency of page utilization, and it would be very inefficient for the operating system or hypervisor to continually scan and clear/reset the “accessed” control bits in PTEs of pages for purposes of measuring memory utilization.